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Add FPGA Duty Cycle support (#1987)
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committed by
Peter Johnson
parent
509819d83f
commit
1d695a1660
119
hal/src/main/native/athena/DutyCycle.cpp
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119
hal/src/main/native/athena/DutyCycle.cpp
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/*----------------------------------------------------------------------------*/
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/* Copyright (c) 2019 FIRST. All Rights Reserved. */
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/* Open Source Software - may be modified and shared by FRC teams. The code */
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/* must be accompanied by the FIRST BSD license file in the root directory of */
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/* the project. */
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/*----------------------------------------------------------------------------*/
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#include "hal/DutyCycle.h"
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#include <memory>
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#include "DigitalInternal.h"
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#include "DutyCycleInternal.h"
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#include "HALInitializer.h"
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#include "PortsInternal.h"
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#include "hal/ChipObject.h"
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#include "hal/Errors.h"
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#include "hal/handles/HandlesInternal.h"
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#include "hal/handles/LimitedHandleResource.h"
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using namespace hal;
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namespace hal {
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LimitedHandleResource<HAL_DutyCycleHandle, DutyCycle, kNumDutyCycles,
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HAL_HandleEnum::DutyCycle>* dutyCycleHandles;
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namespace init {
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void InitializeDutyCycle() {
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static LimitedHandleResource<HAL_DutyCycleHandle, DutyCycle, kNumDutyCycles,
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HAL_HandleEnum::DutyCycle>
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dcH;
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dutyCycleHandles = &dcH;
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}
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} // namespace init
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} // namespace hal
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static constexpr int32_t kScaleFactor = 4e7 - 1;
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extern "C" {
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HAL_DutyCycleHandle HAL_InitializeDutyCycle(HAL_Handle digitalSourceHandle,
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HAL_AnalogTriggerType triggerType,
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int32_t* status) {
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hal::init::CheckInit();
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bool routingAnalogTrigger = false;
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uint8_t routingChannel = 0;
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uint8_t routingModule = 0;
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bool success =
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remapDigitalSource(digitalSourceHandle, triggerType, routingChannel,
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routingModule, routingAnalogTrigger);
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if (!success) {
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*status = HAL_HANDLE_ERROR;
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return HAL_kInvalidHandle;
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}
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HAL_DutyCycleHandle handle = dutyCycleHandles->Allocate();
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if (handle == HAL_kInvalidHandle) {
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*status = NO_AVAILABLE_RESOURCES;
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return HAL_kInvalidHandle;
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}
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auto dutyCycle = dutyCycleHandles->Get(handle);
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uint32_t index = static_cast<uint32_t>(getHandleIndex(handle));
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dutyCycle->dutyCycle.reset(tDutyCycle::create(index, status));
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dutyCycle->dutyCycle->writeSource_AnalogTrigger(routingAnalogTrigger, status);
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dutyCycle->dutyCycle->writeSource_Channel(routingChannel, status);
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dutyCycle->dutyCycle->writeSource_Module(routingModule, status);
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dutyCycle->index = index;
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return handle;
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}
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void HAL_FreeDutyCycle(HAL_DutyCycleHandle dutyCycleHandle) {
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// Just free it, the unique ptr will take care of everything else
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dutyCycleHandles->Free(dutyCycleHandle);
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}
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int32_t HAL_GetDutyCycleFrequency(HAL_DutyCycleHandle dutyCycleHandle,
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int32_t* status) {
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auto dutyCycle = dutyCycleHandles->Get(dutyCycleHandle);
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if (!dutyCycle) {
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*status = HAL_HANDLE_ERROR;
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return 0;
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}
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return dutyCycle->dutyCycle->readFrequency(status);
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}
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double HAL_GetDutyCycleOutput(HAL_DutyCycleHandle dutyCycleHandle,
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int32_t* status) {
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return HAL_GetDutyCycleOutputRaw(dutyCycleHandle, status) / kScaleFactor;
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}
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int32_t HAL_GetDutyCycleOutputRaw(HAL_DutyCycleHandle dutyCycleHandle,
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int32_t* status) {
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auto dutyCycle = dutyCycleHandles->Get(dutyCycleHandle);
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if (!dutyCycle) {
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*status = HAL_HANDLE_ERROR;
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return 0;
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}
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return dutyCycle->dutyCycle->readOutput(status);
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}
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int32_t HAL_GetDutyCycleOutputScaleFactor(HAL_DutyCycleHandle dutyCycleHandle,
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int32_t* status) {
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return kScaleFactor;
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}
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int32_t HAL_GetDutyCycleFPGAIndex(HAL_DutyCycleHandle dutyCycleHandle,
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int32_t* status) {
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auto dutyCycle = dutyCycleHandles->Get(dutyCycleHandle);
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if (!dutyCycle) {
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*status = HAL_HANDLE_ERROR;
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return -1;
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}
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return dutyCycle->index;
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}
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} // extern "C"
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