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[hal,wpilib] Remove a ton of things related to the FPGA (#7846)

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Co-authored-by: Gold856 <117957790+Gold856@users.noreply.github.com>
This commit is contained in:
Thad House
2026-04-17 19:38:25 -07:00
committed by GitHub
parent fdb454a6b1
commit 6cb6903780
73 changed files with 69 additions and 1834 deletions
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10
wpilibc/src/main/python/semiwrap/AnalogInput.yml
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@@ -8,18 +8,8 @@ classes:
methods:
AnalogInput:
GetValue:
GetAverageValue:
GetVoltage:
GetAverageVoltage:
GetChannel:
SetAverageBits:
GetAverageBits:
SetOversampleBits:
GetOversampleBits:
GetLSBWeight:
GetOffset:
SetSampleRate:
GetSampleRate:
SetSimDevice:
InitSendable:

7
wpilibc/src/main/python/semiwrap/SensorUtil.yml
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@@ -2,11 +2,6 @@ classes:
wpi::SensorUtil:
nodelete: true
methods:
CheckDigitalChannel:
CheckPWMChannel:
CheckAnalogInputChannel:
GetDefaultCTREPCMModule:
GetDefaultREVPHModule:
GetNumDigitalChannels:
GetNumAnalogInputs:
GetNumPwmChannels:
GetNumSmartIoPorts:

6
wpilibc/src/main/python/semiwrap/simulation/AnalogInputSim.yml
View File

@@ -13,12 +13,6 @@ classes:
RegisterInitializedCallback:
GetInitialized:
SetInitialized:
RegisterAverageBitsCallback:
GetAverageBits:
SetAverageBits:
RegisterOversampleBitsCallback:
GetOversampleBits:
SetOversampleBits:
RegisterVoltageCallback:
GetVoltage:
SetVoltage: