Team2890/allwpilib
4
0
Fork 0
mirror of https://github.com/wpilibsuite/allwpilib synced 2026-06-29 02:21:44 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update headers and .sos to v15 image + most API changes

Browse Source 
Java still does not work

Change-Id: I172ac401a07b6703909068f82b7b6cc67e6075c0
This commit is contained in:
Thomas Clark
2014-10-05 17:17:59 -04:00
parent 6089722c4f
commit 7e9f183cf9
87 changed files with 2812 additions and 2667 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hal/lib/Athena/FRC_FPGA_ChipObject/FRC_FPGA_ChipObject_Aliases.h
View File

@@ -4,7 +4,7 @@
#ifndef __FRC_FPGA_ChipObject_Aliases_h__
#define __FRC_FPGA_ChipObject_Aliases_h__
#define nInvariantFPGANamespace nFRC_C0EF_1_1_0
#define nRuntimeFPGANamespace nFRC_2012_1_6_4
#define nInvariantFPGANamespace nFRC_C0EF_1_1_0
#endif // __FRC_FPGA_ChipObject_Aliases_h__

2
hal/lib/Athena/FRC_FPGA_ChipObject/RoboRIO_FRC_ChipObject_Aliases.h
View File

@@ -4,6 +4,6 @@
#ifndef __RoboRIO_FRC_ChipObject_Aliases_h__
#define __RoboRIO_FRC_ChipObject_Aliases_h__
#define nRoboRIO_FPGANamespace nFRC_2015_1_0_8
#define nRoboRIO_FPGANamespace nFRC_2015_1_0_9
#endif // __RoboRIO_FRC_ChipObject_Aliases_h__

4762
hal/lib/Athena/FRC_FPGA_ChipObject/fpgainterfacecapi/NiFpga.h
View File

File diff suppressed because it is too large Load Diff

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/nInterfaceGlobals.h
View File

@@ -1,15 +1,15 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_nInterfaceGlobals_h__
#define __nFRC_2015_1_0_8_nInterfaceGlobals_h__
#ifndef __nFRC_2015_1_0_9_nInterfaceGlobals_h__
#define __nFRC_2015_1_0_9_nInterfaceGlobals_h__
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
extern unsigned int g_currentTargetClass;
}
}
#endif // __nFRC_2015_1_0_8_nInterfaceGlobals_h__
#endif // __nFRC_2015_1_0_9_nInterfaceGlobals_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tAI.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_AI_h__
#define __nFRC_2015_1_0_8_AI_h__
#ifndef __nFRC_2015_1_0_9_AI_h__
#define __nFRC_2015_1_0_9_AI_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tAI
@@ -140,4 +140,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_AI_h__
#endif // __nFRC_2015_1_0_9_AI_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tAO.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_AO_h__
#define __nFRC_2015_1_0_8_AO_h__
#ifndef __nFRC_2015_1_0_9_AO_h__
#define __nFRC_2015_1_0_9_AO_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tAO
@@ -47,4 +47,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_AO_h__
#endif // __nFRC_2015_1_0_9_AO_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tAccel.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Accel_h__
#define __nFRC_2015_1_0_8_Accel_h__
#ifndef __nFRC_2015_1_0_9_Accel_h__
#define __nFRC_2015_1_0_9_Accel_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tAccel
@@ -99,4 +99,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Accel_h__
#endif // __nFRC_2015_1_0_9_Accel_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tAccumulator.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Accumulator_h__
#define __nFRC_2015_1_0_8_Accumulator_h__
#ifndef __nFRC_2015_1_0_9_Accumulator_h__
#define __nFRC_2015_1_0_9_Accumulator_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tAccumulator
@@ -84,4 +84,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Accumulator_h__
#endif // __nFRC_2015_1_0_9_Accumulator_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tAlarm.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Alarm_h__
#define __nFRC_2015_1_0_8_Alarm_h__
#ifndef __nFRC_2015_1_0_9_Alarm_h__
#define __nFRC_2015_1_0_9_Alarm_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tAlarm
@@ -54,4 +54,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Alarm_h__
#endif // __nFRC_2015_1_0_9_Alarm_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tAnalogTrigger.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_AnalogTrigger_h__
#define __nFRC_2015_1_0_8_AnalogTrigger_h__
#ifndef __nFRC_2015_1_0_9_AnalogTrigger_h__
#define __nFRC_2015_1_0_9_AnalogTrigger_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tAnalogTrigger
@@ -126,4 +126,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_AnalogTrigger_h__
#endif // __nFRC_2015_1_0_9_AnalogTrigger_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tBIST.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_BIST_h__
#define __nFRC_2015_1_0_8_BIST_h__
#ifndef __nFRC_2015_1_0_9_BIST_h__
#define __nFRC_2015_1_0_9_BIST_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tBIST
@@ -87,4 +87,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_BIST_h__
#endif // __nFRC_2015_1_0_9_BIST_h__

16
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tCounter.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Counter_h__
#define __nFRC_2015_1_0_8_Counter_h__
#ifndef __nFRC_2015_1_0_9_Counter_h__
#define __nFRC_2015_1_0_9_Counter_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tCounter
@@ -56,21 +56,21 @@ public:
unsigned IndexSource_Module : 1;
unsigned IndexSource_AnalogTrigger : 1;
unsigned IndexActiveHigh : 1;
unsigned IndexEdgeSensitive : 1;
unsigned UpRisingEdge : 1;
unsigned UpFallingEdge : 1;
unsigned DownRisingEdge : 1;
unsigned DownFallingEdge : 1;
unsigned Mode : 2;
unsigned PulseLengthThreshold : 6;
unsigned Enable : 1;
#else
unsigned Enable : 1;
unsigned PulseLengthThreshold : 6;
unsigned Mode : 2;
unsigned DownFallingEdge : 1;
unsigned DownRisingEdge : 1;
unsigned UpFallingEdge : 1;
unsigned UpRisingEdge : 1;
unsigned IndexEdgeSensitive : 1;
unsigned IndexActiveHigh : 1;
unsigned IndexSource_AnalogTrigger : 1;
unsigned IndexSource_Module : 1;
@@ -147,13 +147,13 @@ public:
virtual void writeConfig_IndexSource_Module(unsigned char value, tRioStatusCode *status) = 0;
virtual void writeConfig_IndexSource_AnalogTrigger(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_IndexActiveHigh(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_IndexEdgeSensitive(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_UpRisingEdge(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_UpFallingEdge(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_DownRisingEdge(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_DownFallingEdge(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_Mode(unsigned char value, tRioStatusCode *status) = 0;
virtual void writeConfig_PulseLengthThreshold(unsigned short value, tRioStatusCode *status) = 0;
virtual void writeConfig_Enable(bool value, tRioStatusCode *status) = 0;
virtual tConfig readConfig(tRioStatusCode *status) = 0;
virtual unsigned char readConfig_UpSource_Channel(tRioStatusCode *status) = 0;
virtual unsigned char readConfig_UpSource_Module(tRioStatusCode *status) = 0;
@@ -165,13 +165,13 @@ public:
virtual unsigned char readConfig_IndexSource_Module(tRioStatusCode *status) = 0;
virtual bool readConfig_IndexSource_AnalogTrigger(tRioStatusCode *status) = 0;
virtual bool readConfig_IndexActiveHigh(tRioStatusCode *status) = 0;
virtual bool readConfig_IndexEdgeSensitive(tRioStatusCode *status) = 0;
virtual bool readConfig_UpRisingEdge(tRioStatusCode *status) = 0;
virtual bool readConfig_UpFallingEdge(tRioStatusCode *status) = 0;
virtual bool readConfig_DownRisingEdge(tRioStatusCode *status) = 0;
virtual bool readConfig_DownFallingEdge(tRioStatusCode *status) = 0;
virtual unsigned char readConfig_Mode(tRioStatusCode *status) = 0;
virtual unsigned short readConfig_PulseLengthThreshold(tRioStatusCode *status) = 0;
virtual bool readConfig_Enable(tRioStatusCode *status) = 0;
typedef enum
@@ -216,4 +216,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Counter_h__
#endif // __nFRC_2015_1_0_9_Counter_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tDIO.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_DIO_h__
#define __nFRC_2015_1_0_8_DIO_h__
#ifndef __nFRC_2015_1_0_9_DIO_h__
#define __nFRC_2015_1_0_9_DIO_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tDIO
@@ -245,4 +245,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_DIO_h__
#endif // __nFRC_2015_1_0_9_DIO_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tDMA.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_DMA_h__
#define __nFRC_2015_1_0_8_DMA_h__
#ifndef __nFRC_2015_1_0_9_DMA_h__
#define __nFRC_2015_1_0_9_DMA_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tDMA
@@ -185,4 +185,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_DMA_h__
#endif // __nFRC_2015_1_0_9_DMA_h__

16
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tEncoder.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Encoder_h__
#define __nFRC_2015_1_0_8_Encoder_h__
#ifndef __nFRC_2015_1_0_9_Encoder_h__
#define __nFRC_2015_1_0_9_Encoder_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tEncoder
@@ -56,11 +56,11 @@ public:
unsigned IndexSource_Module : 1;
unsigned IndexSource_AnalogTrigger : 1;
unsigned IndexActiveHigh : 1;
unsigned IndexEdgeSensitive : 1;
unsigned Reverse : 1;
unsigned Enable : 1;
#else
unsigned Enable : 1;
unsigned Reverse : 1;
unsigned IndexEdgeSensitive : 1;
unsigned IndexActiveHigh : 1;
unsigned IndexSource_AnalogTrigger : 1;
unsigned IndexSource_Module : 1;
@@ -137,8 +137,8 @@ public:
virtual void writeConfig_IndexSource_Module(unsigned char value, tRioStatusCode *status) = 0;
virtual void writeConfig_IndexSource_AnalogTrigger(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_IndexActiveHigh(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_IndexEdgeSensitive(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_Reverse(bool value, tRioStatusCode *status) = 0;
virtual void writeConfig_Enable(bool value, tRioStatusCode *status) = 0;
virtual tConfig readConfig(tRioStatusCode *status) = 0;
virtual unsigned char readConfig_ASource_Channel(tRioStatusCode *status) = 0;
virtual unsigned char readConfig_ASource_Module(tRioStatusCode *status) = 0;
@@ -150,8 +150,8 @@ public:
virtual unsigned char readConfig_IndexSource_Module(tRioStatusCode *status) = 0;
virtual bool readConfig_IndexSource_AnalogTrigger(tRioStatusCode *status) = 0;
virtual bool readConfig_IndexActiveHigh(tRioStatusCode *status) = 0;
virtual bool readConfig_IndexEdgeSensitive(tRioStatusCode *status) = 0;
virtual bool readConfig_Reverse(tRioStatusCode *status) = 0;
virtual bool readConfig_Enable(tRioStatusCode *status) = 0;
typedef enum
@@ -196,4 +196,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Encoder_h__
#endif // __nFRC_2015_1_0_9_Encoder_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tGlobal.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Global_h__
#define __nFRC_2015_1_0_8_Global_h__
#ifndef __nFRC_2015_1_0_9_Global_h__
#define __nFRC_2015_1_0_9_Global_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tGlobal
@@ -101,4 +101,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Global_h__
#endif // __nFRC_2015_1_0_9_Global_h__

19
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tInterrupt.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Interrupt_h__
#define __nFRC_2015_1_0_8_Interrupt_h__
#ifndef __nFRC_2015_1_0_9_Interrupt_h__
#define __nFRC_2015_1_0_9_Interrupt_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tInterrupt
@@ -54,9 +54,9 @@ public:
typedef enum
{
} tTimeStamp_IfaceConstants;
} tFallingTimeStamp_IfaceConstants;
virtual unsigned int readTimeStamp(tRioStatusCode *status) = 0;
virtual unsigned int readFallingTimeStamp(tRioStatusCode *status) = 0;
typedef enum
@@ -79,6 +79,13 @@ public:
virtual bool readConfig_WaitForAck(tRioStatusCode *status) = 0;
typedef enum
{
} tRisingTimeStamp_IfaceConstants;
virtual unsigned int readRisingTimeStamp(tRioStatusCode *status) = 0;
@@ -90,4 +97,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Interrupt_h__
#endif // __nFRC_2015_1_0_9_Interrupt_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tPWM.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_PWM_h__
#define __nFRC_2015_1_0_8_PWM_h__
#ifndef __nFRC_2015_1_0_9_PWM_h__
#define __nFRC_2015_1_0_9_PWM_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tPWM
@@ -117,4 +117,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_PWM_h__
#endif // __nFRC_2015_1_0_9_PWM_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tPower.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Power_h__
#define __nFRC_2015_1_0_8_Power_h__
#ifndef __nFRC_2015_1_0_9_Power_h__
#define __nFRC_2015_1_0_9_Power_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tPower
@@ -214,4 +214,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Power_h__
#endif // __nFRC_2015_1_0_9_Power_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tRelay.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_Relay_h__
#define __nFRC_2015_1_0_8_Relay_h__
#ifndef __nFRC_2015_1_0_9_Relay_h__
#define __nFRC_2015_1_0_9_Relay_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tRelay
@@ -65,4 +65,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_Relay_h__
#endif // __nFRC_2015_1_0_9_Relay_h__

8
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tSPI.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_SPI_h__
#define __nFRC_2015_1_0_8_SPI_h__
#ifndef __nFRC_2015_1_0_9_SPI_h__
#define __nFRC_2015_1_0_9_SPI_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tSPI
@@ -65,4 +65,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_SPI_h__
#endif // __nFRC_2015_1_0_9_SPI_h__

15
hal/lib/Athena/FRC_FPGA_ChipObject/nRoboRIO_FPGANamespace/tSysWatchdog.h
View File

@@ -1,14 +1,14 @@
// Copyright (c) National Instruments 2008. All Rights Reserved.
// Do Not Edit... this file is generated!
#ifndef __nFRC_2015_1_0_8_SysWatchdog_h__
#define __nFRC_2015_1_0_8_SysWatchdog_h__
#ifndef __nFRC_2015_1_0_9_SysWatchdog_h__
#define __nFRC_2015_1_0_9_SysWatchdog_h__
#include "tSystemInterface.h"
namespace nFPGA
{
namespace nFRC_2015_1_0_8
namespace nFRC_2015_1_0_9
{
class tSysWatchdog
@@ -88,6 +88,13 @@ public:
virtual unsigned int readTimer(tRioStatusCode *status) = 0;
typedef enum
{
} tForcedKills_IfaceConstants;
virtual unsigned short readForcedKills(tRioStatusCode *status) = 0;
private:
@@ -98,4 +105,4 @@ private:
}
}
#endif // __nFRC_2015_1_0_8_SysWatchdog_h__
#endif // __nFRC_2015_1_0_9_SysWatchdog_h__

17
hal/lib/Athena/FRC_FPGA_ChipObject/tDMAChannelDescriptor.h Normal file
View File

@@ -0,0 +1,17 @@
// Describes the information needed to configure a DMA channel.
// Copyright (c) National Instruments 2008. All Rights Reserved.
#include <stdint.h>
#ifndef __tDMAChannelDescriptor_h__
#define __tDMAChannelDescriptor_h__
struct tDMAChannelDescriptor
{
uint32_t channel;
uint32_t baseAddress;
uint32_t depth;
bool targetToHost;
};
#endif // __tDMAChannelDescriptor_h__

33
hal/lib/Athena/FRC_FPGA_ChipObject/tDMAManager.h
View File

@@ -1,46 +1,41 @@
// Class for handling DMA transters.
// Class for handling DMA transfers.
// Copyright (c) National Instruments 2008. All Rights Reserved.
#ifndef __tDMAManager_h__
#define __tDMAManager_h__
#include "tSystem.h"
#include <stdint.h>
namespace nFPGA
{
// TODO: Implement DMA Manager
/*
class tDMAManager : public tSystem
{
public:
tDMAManager(tNIRIO_u32 dmaChannel, tNIRIO_u32 hostBufferSize, tRioStatusCode *status);
tDMAManager(uint32_t dmaChannel, uint32_t hostBufferSize, tRioStatusCode *status);
~tDMAManager();
void start(tRioStatusCode *status);
void stop(tRioStatusCode *status);
bool isStarted() {return _started;}
void read(
tNIRIO_u32* buf,
tNIRIO_u32 num,
tNIRIO_u32 timeout,
tNIRIO_u32* read,
tNIRIO_u32* remaining,
uint32_t* buf,
size_t num,
uint32_t timeout,
size_t* remaining,
tRioStatusCode *status);
void write(
tNIRIO_u32* buf,
tNIRIO_u32 num,
tNIRIO_u32 timeout,
tNIRIO_u32* remaining,
uint32_t* buf,
size_t num,
uint32_t timeout,
size_t* remaining,
tRioStatusCode *status);
private:
bool _started;
tNIRIO_u32 _dmaChannel;
tNIRIO_u32 _hostBufferSize;
tDMAChannelDescriptor const *_dmaChannelDescriptor;
uint32_t _dmaChannel;
uint32_t _hostBufferSize;
};
*/
}
#endif // __tDMAManager_h__

5
hal/lib/Athena/FRC_FPGA_ChipObject/tInterruptManager.h
View File

@@ -28,11 +28,11 @@ public:
tInterruptManager(uint32_t interruptMask, bool watcher, tRioStatusCode *status);
~tInterruptManager();
void registerHandler(tInterruptHandler handler, void *param, tRioStatusCode *status);
uint32_t watch(int32_t timeoutInMs, tRioStatusCode *status);
uint32_t watch(int32_t timeoutInMs, bool ignorePrevious, tRioStatusCode *status);
void enable(tRioStatusCode *status);
void disable(tRioStatusCode *status);
bool isEnabled(tRioStatusCode *status);
private:
public:
class tInterruptThread;
friend class tInterruptThread;
void handler();
@@ -58,4 +58,3 @@ private:
#endif // __tInterruptManager_h__

1
hal/lib/Athena/FRC_FPGA_ChipObject/tSystem.h
View File

@@ -20,6 +20,7 @@ public:
tSystem(tRioStatusCode *status);
~tSystem();
void getFpgaGuid(uint32_t *guid_ptr, tRioStatusCode *status);
void reset(tRioStatusCode *status);
protected:
static NiFpga_Session _DeviceHandle;

2
hal/lib/Athena/FRC_FPGA_ChipObject/tSystemInterface.h
View File

@@ -18,8 +18,10 @@ public:
virtual void getHardwareFpgaSignature(uint32_t *guid_ptr, tRioStatusCode *status)=0;
virtual uint32_t getLVHandle(tRioStatusCode *status)=0;
virtual uint32_t getHandle()=0;
virtual void reset(tRioStatusCode *status)=0;
};
}
#endif // __tSystemInterface_h__