Team2890/allwpilib
4
0
Fork 0
mirror of https://github.com/wpilibsuite/allwpilib synced 2026-06-30 02:31:44 +00:00
Code Issues Packages Projects Releases Wiki Activity

Add AddressableLED (#2092)

Browse Source
This commit is contained in:
Thad House
2019-11-17 16:39:38 -08:00
committed by Peter Johnson
parent 59507b12dc
commit 8ed2059074
20 changed files with 991 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
hal/src/main/native/athena/DigitalInternal.h
View File

@@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------*/
/* Copyright (c) 2016-2018 FIRST. All Rights Reserved. */
/* Copyright (c) 2016-2019 FIRST. All Rights Reserved. */
/* Open Source Software - may be modified and shared by FRC teams. The code */
/* must be accompanied by the FIRST BSD license file in the root directory of */
/* the project. */
@@ -96,6 +96,20 @@ bool remapDigitalSource(HAL_Handle digitalSourceHandle,
HAL_AnalogTriggerType analogTriggerType,
uint8_t& channel, uint8_t& module, bool& analogTrigger);
/**
* Remap the Digital Channel to map to the bitfield channel of the FPGA
*/
constexpr int32_t remapDigitalChannelToBitfieldChannel(int32_t channel) {
// First 10 are headers
if (channel < kNumDigitalHeaders) return channel;
// 2nd group of 16 are mxp. So if mxp port, add 6, since they start at 10
else if (channel < kNumDigitalMXPChannels)
return channel + 6;
// Assume SPI, so remove MXP channels
else
return channel - kNumDigitalMXPChannels;
}
/**
* Map DIO channel numbers from their physical number (10 to 26) to their
* position in the bit field.