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Fix CAN API timing out incorrectly (#1497)

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HAL_GetFPGATime returns 0 if it starts with a non zero status.

Always use monotonic clock for CAN times, rather then trying to sync FPGA.

Change timeout from 50 ms to 100 ms.
This commit is contained in:
Thad House
2018-12-29 13:57:23 -08:00
committed by Peter Johnson
parent 300eeb330d
commit d46ce13ffe
5 changed files with 57 additions and 84 deletions
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2
hal/src/main/native/athena/PDP.cpp
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@@ -31,7 +31,7 @@ static constexpr int32_t StatusEnergy = 0x5D;
static constexpr int32_t Control1 = 0x70;
static constexpr int32_t TimeoutMs = 50;
static constexpr int32_t TimeoutMs = 100;
static constexpr int32_t StatusPeriodMs = 25;
/* encoder/decoders */