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https://github.com/wpilibsuite/allwpilib
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Split HAL Digital Implementation files (#59)
Split to match the new headers. Uses a namespace 'hal' for internal functions and globals. SPIAccumulator merged back into SPI header, as it was not a good split. Analog accumulator will move back to analog input when the analog split is done.
This commit is contained in:
Thad House
committed by
Peter Johnson
Peter Johnson
parent
305ab08f1c
commit
da6b8c7ae1
423
hal/lib/athena/DIO.cpp
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423
hal/lib/athena/DIO.cpp
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/*----------------------------------------------------------------------------*/
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/* Copyright (c) FIRST 2016. All Rights Reserved. */
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/* Open Source Software - may be modified and shared by FRC teams. The code */
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/* must be accompanied by the FIRST BSD license file in the root directory of */
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/* the project. */
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/*----------------------------------------------------------------------------*/
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#include "HAL/DIO.h"
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#include <math.h>
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#include "DigitalInternal.h"
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static_assert(sizeof(uint32_t) <= sizeof(void*),
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"This file shoves uint32_ts into pointers.");
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using namespace hal;
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// Create a mutex to protect changes to the digital output values
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static priority_recursive_mutex digitalDIOMutex;
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extern "C" {
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/**
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* Create a new instance of a digital port.
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*/
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void* initializeDigitalPort(void* port_pointer, int32_t* status) {
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initializeDigital(status);
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Port* port = (Port*)port_pointer;
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// Initialize port structure
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DigitalPort* digital_port = new DigitalPort();
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digital_port->port = *port;
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return digital_port;
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}
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void freeDigitalPort(void* digital_port_pointer) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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delete port;
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}
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/**
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* Allocate a DO PWM Generator.
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* Allocate PWM generators so that they are not accidentally reused.
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*
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* @return PWM Generator refnum
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*/
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void* allocatePWM(int32_t* status) {
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return (void*)DO_PWMGenerators->Allocate("DO_PWM");
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}
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/**
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* Free the resource associated with a DO PWM generator.
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*
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* @param pwmGenerator The pwmGen to free that was allocated with
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* AllocateDO_PWM()
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*/
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void freePWM(void* pwmGenerator, int32_t* status) {
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uint32_t id = (uint32_t)pwmGenerator;
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if (id == ~0ul) return;
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DO_PWMGenerators->Free(id);
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}
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/**
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* Change the frequency of the DO PWM generator.
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*
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* The valid range is from 0.6 Hz to 19 kHz. The frequency resolution is
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* logarithmic.
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*
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* @param rate The frequency to output all digital output PWM signals.
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*/
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void setPWMRate(double rate, int32_t* status) {
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// Currently rounding in the log rate domain... heavy weight toward picking a
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// higher freq.
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// TODO: Round in the linear rate domain.
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uint8_t pwmPeriodPower = (uint8_t)(
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log(1.0 / (pwmSystem->readLoopTiming(status) * 0.25E-6 * rate)) /
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log(2.0) +
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0.5);
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digitalSystem->writePWMPeriodPower(pwmPeriodPower, status);
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}
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/**
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* Configure the duty-cycle of the PWM generator
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*
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* @param pwmGenerator The generator index reserved by AllocateDO_PWM()
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* @param dutyCycle The percent duty cycle to output [0..1].
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*/
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void setPWMDutyCycle(void* pwmGenerator, double dutyCycle, int32_t* status) {
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uint32_t id = (uint32_t)pwmGenerator;
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if (id == ~0ul) return;
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if (dutyCycle > 1.0) dutyCycle = 1.0;
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if (dutyCycle < 0.0) dutyCycle = 0.0;
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float rawDutyCycle = 256.0 * dutyCycle;
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if (rawDutyCycle > 255.5) rawDutyCycle = 255.5;
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{
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std::lock_guard<priority_recursive_mutex> sync(digitalPwmMutex);
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uint8_t pwmPeriodPower = digitalSystem->readPWMPeriodPower(status);
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if (pwmPeriodPower < 4) {
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// The resolution of the duty cycle drops close to the highest
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// frequencies.
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rawDutyCycle = rawDutyCycle / pow(2.0, 4 - pwmPeriodPower);
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}
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if (id < 4)
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digitalSystem->writePWMDutyCycleA(id, (uint8_t)rawDutyCycle, status);
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else
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digitalSystem->writePWMDutyCycleB(id - 4, (uint8_t)rawDutyCycle, status);
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}
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}
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/**
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* Configure which DO channel the PWM signal is output on
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*
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* @param pwmGenerator The generator index reserved by AllocateDO_PWM()
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* @param channel The Digital Output channel to output on
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*/
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void setPWMOutputChannel(void* pwmGenerator, uint32_t pin, int32_t* status) {
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uint32_t id = (uint32_t)pwmGenerator;
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if (id > 5) return;
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digitalSystem->writePWMOutputSelect(id, pin, status);
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}
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/**
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* Allocate Digital I/O channels.
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* Allocate channels so that they are not accidently reused. Also the direction
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* is set at the time of the allocation.
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*
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* @param channel The Digital I/O channel
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* @param input If true open as input; if false open as output
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* @return Was successfully allocated
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*/
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bool allocateDIO(void* digital_port_pointer, bool input, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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char buf[64];
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snprintf(buf, 64, "DIO %d", port->port.pin);
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if (DIOChannels->Allocate(port->port.pin, buf) == ~0ul) {
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*status = RESOURCE_IS_ALLOCATED;
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return false;
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}
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{
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std::lock_guard<priority_recursive_mutex> sync(digitalDIOMutex);
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tDIO::tOutputEnable outputEnable = digitalSystem->readOutputEnable(status);
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if (port->port.pin < kNumHeaders) {
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uint32_t bitToSet = 1 << port->port.pin;
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if (input) {
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outputEnable.Headers =
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outputEnable.Headers & (~bitToSet); // clear the bit for read
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} else {
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outputEnable.Headers =
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outputEnable.Headers | bitToSet; // set the bit for write
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}
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} else {
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uint32_t bitToSet = 1 << remapMXPChannel(port->port.pin);
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// Disable special functions on this pin
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short specialFunctions =
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digitalSystem->readEnableMXPSpecialFunction(status);
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digitalSystem->writeEnableMXPSpecialFunction(specialFunctions & ~bitToSet,
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status);
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if (input) {
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outputEnable.MXP =
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outputEnable.MXP & (~bitToSet); // clear the bit for read
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} else {
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outputEnable.MXP =
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outputEnable.MXP | bitToSet; // set the bit for write
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}
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}
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digitalSystem->writeOutputEnable(outputEnable, status);
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}
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return true;
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}
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/**
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* Free the resource associated with a digital I/O channel.
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*
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* @param channel The Digital I/O channel to free
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*/
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void freeDIO(void* digital_port_pointer, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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if (!port) return;
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DIOChannels->Free(port->port.pin);
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}
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/**
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* Write a digital I/O bit to the FPGA.
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* Set a single value on a digital I/O channel.
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*
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* @param channel The Digital I/O channel
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* @param value The state to set the digital channel (if it is configured as an
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* output)
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*/
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void setDIO(void* digital_port_pointer, short value, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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if (value != 0 && value != 1) {
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if (value != 0) value = 1;
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}
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{
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std::lock_guard<priority_recursive_mutex> sync(digitalDIOMutex);
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tDIO::tDO currentDIO = digitalSystem->readDO(status);
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if (port->port.pin < kNumHeaders) {
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if (value == 0) {
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currentDIO.Headers = currentDIO.Headers & ~(1 << port->port.pin);
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} else if (value == 1) {
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currentDIO.Headers = currentDIO.Headers | (1 << port->port.pin);
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}
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} else {
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if (value == 0) {
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currentDIO.MXP =
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currentDIO.MXP & ~(1 << remapMXPChannel(port->port.pin));
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} else if (value == 1) {
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currentDIO.MXP =
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currentDIO.MXP | (1 << remapMXPChannel(port->port.pin));
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}
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uint32_t bitToSet = 1 << remapMXPChannel(port->port.pin);
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short specialFunctions =
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digitalSystem->readEnableMXPSpecialFunction(status);
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digitalSystem->writeEnableMXPSpecialFunction(specialFunctions & ~bitToSet,
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status);
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}
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digitalSystem->writeDO(currentDIO, status);
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}
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}
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/**
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* Read a digital I/O bit from the FPGA.
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* Get a single value from a digital I/O channel.
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*
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* @param channel The digital I/O channel
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* @return The state of the specified channel
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*/
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bool getDIO(void* digital_port_pointer, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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tDIO::tDI currentDIO = digitalSystem->readDI(status);
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// Shift 00000001 over channel-1 places.
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// AND it against the currentDIO
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// if it == 0, then return false
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// else return true
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if (port->port.pin < kNumHeaders) {
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return ((currentDIO.Headers >> port->port.pin) & 1) != 0;
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} else {
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// Disable special functions
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uint32_t bitToSet = 1 << remapMXPChannel(port->port.pin);
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short specialFunctions =
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digitalSystem->readEnableMXPSpecialFunction(status);
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digitalSystem->writeEnableMXPSpecialFunction(specialFunctions & ~bitToSet,
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status);
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return ((currentDIO.MXP >> remapMXPChannel(port->port.pin)) & 1) != 0;
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}
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}
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/**
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* Read the direction of a the Digital I/O lines
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* A 1 bit means output and a 0 bit means input.
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*
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* @param channel The digital I/O channel
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* @return The direction of the specified channel
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*/
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bool getDIODirection(void* digital_port_pointer, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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tDIO::tOutputEnable currentOutputEnable =
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digitalSystem->readOutputEnable(status);
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// Shift 00000001 over port->port.pin-1 places.
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// AND it against the currentOutputEnable
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// if it == 0, then return false
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// else return true
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if (port->port.pin < kNumHeaders) {
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return ((currentOutputEnable.Headers >> port->port.pin) & 1) != 0;
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} else {
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return ((currentOutputEnable.MXP >> remapMXPChannel(port->port.pin)) & 1) !=
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0;
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}
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}
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/**
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* Generate a single pulse.
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* Write a pulse to the specified digital output channel. There can only be a
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* single pulse going at any time.
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*
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* @param channel The Digital Output channel that the pulse should be output on
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* @param pulseLength The active length of the pulse (in seconds)
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*/
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void pulse(void* digital_port_pointer, double pulseLength, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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tDIO::tPulse pulse;
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if (port->port.pin < kNumHeaders) {
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pulse.Headers = 1 << port->port.pin;
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} else {
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pulse.MXP = 1 << remapMXPChannel(port->port.pin);
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}
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digitalSystem->writePulseLength(
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(uint8_t)(1.0e9 * pulseLength / (pwmSystem->readLoopTiming(status) * 25)),
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status);
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digitalSystem->writePulse(pulse, status);
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}
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/**
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* Check a DIO line to see if it is currently generating a pulse.
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*
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* @return A pulse is in progress
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*/
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bool isPulsing(void* digital_port_pointer, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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tDIO::tPulse pulseRegister = digitalSystem->readPulse(status);
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if (port->port.pin < kNumHeaders) {
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return (pulseRegister.Headers & (1 << port->port.pin)) != 0;
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} else {
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return (pulseRegister.MXP & (1 << remapMXPChannel(port->port.pin))) != 0;
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}
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}
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/**
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* Check if any DIO line is currently generating a pulse.
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*
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* @return A pulse on some line is in progress
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*/
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bool isAnyPulsing(int32_t* status) {
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tDIO::tPulse pulseRegister = digitalSystem->readPulse(status);
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return pulseRegister.Headers != 0 && pulseRegister.MXP != 0;
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}
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/**
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* Write the filter index from the FPGA.
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* Set the filter index used to filter out short pulses.
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*
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* @param digital_port_pointer The digital I/O channel
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* @param filter_index The filter index. Must be in the range 0 - 3,
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* where 0 means "none" and 1 - 3 means filter # filter_index - 1.
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*/
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void setFilterSelect(void* digital_port_pointer, int filter_index,
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int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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std::lock_guard<priority_recursive_mutex> sync(digitalDIOMutex);
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if (port->port.pin < kNumHeaders) {
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digitalSystem->writeFilterSelectHdr(port->port.pin, filter_index, status);
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} else {
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digitalSystem->writeFilterSelectMXP(remapMXPChannel(port->port.pin),
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filter_index, status);
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}
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}
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/**
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* Read the filter index from the FPGA.
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* Get the filter index used to filter out short pulses.
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*
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* @param digital_port_pointer The digital I/O channel
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* @return filter_index The filter index. Must be in the range 0 - 3,
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* where 0 means "none" and 1 - 3 means filter # filter_index - 1.
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*/
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int getFilterSelect(void* digital_port_pointer, int32_t* status) {
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DigitalPort* port = (DigitalPort*)digital_port_pointer;
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std::lock_guard<priority_recursive_mutex> sync(digitalDIOMutex);
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if (port->port.pin < kNumHeaders) {
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return digitalSystem->readFilterSelectHdr(port->port.pin, status);
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} else {
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return digitalSystem->readFilterSelectMXP(remapMXPChannel(port->port.pin),
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status);
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}
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}
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/**
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* Set the filter period for the specified filter index.
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*
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* Set the filter period in FPGA cycles. Even though there are 2 different
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* filter index domains (MXP vs HDR), ignore that distinction for now since it
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* compilicates the interface. That can be changed later.
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*
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* @param filter_index The filter index, 0 - 2.
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* @param value The number of cycles that the signal must not transition to be
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* counted as a transition.
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*/
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void setFilterPeriod(int filter_index, uint32_t value, int32_t* status) {
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std::lock_guard<priority_recursive_mutex> sync(digitalDIOMutex);
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digitalSystem->writeFilterPeriodHdr(filter_index, value, status);
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if (*status == 0) {
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digitalSystem->writeFilterPeriodMXP(filter_index, value, status);
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}
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}
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/**
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* Get the filter period for the specified filter index.
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*
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* Get the filter period in FPGA cycles. Even though there are 2 different
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* filter index domains (MXP vs HDR), ignore that distinction for now since it
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* compilicates the interface. Set status to NiFpga_Status_SoftwareFault if the
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* filter values miss-match.
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*
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* @param filter_index The filter index, 0 - 2.
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* @param value The number of cycles that the signal must not transition to be
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* counted as a transition.
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*/
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uint32_t getFilterPeriod(int filter_index, int32_t* status) {
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uint32_t hdr_period = 0;
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uint32_t mxp_period = 0;
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{
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std::lock_guard<priority_recursive_mutex> sync(digitalDIOMutex);
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hdr_period = digitalSystem->readFilterPeriodHdr(filter_index, status);
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if (*status == 0) {
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mxp_period = digitalSystem->readFilterPeriodMXP(filter_index, status);
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}
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}
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if (hdr_period != mxp_period) {
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*status = NiFpga_Status_SoftwareFault;
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return -1;
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}
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return hdr_period;
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}
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}
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