[hal, wpilib] Remove DigitalGlitchFilter (#7725)

This commit is contained in:
Thad House
2025-01-23 21:44:18 -08:00
committed by GitHub
parent 5a6c895b87
commit e2b6beb28a
10 changed files with 0 additions and 722 deletions

View File

@@ -1,65 +0,0 @@
// Copyright (c) FIRST and other WPILib contributors.
// Open Source Software; you can modify and/or share it under the terms of
// the WPILib BSD license file in the root directory of this project.
package edu.wpi.first.hal;
/**
* Digital Glitch Filter JNI functions.
*
* @see "hal/DIO.h"
*/
public class DigitalGlitchFilterJNI extends JNIWrapper {
/**
* Writes the filter index from the FPGA.
*
* <p>Set the filter index used to filter out short pulses.
*
* @param digitalPortHandle the digital port handle
* @param filterIndex the filter index (Must be in the range 0 - 3, where 0 means "none" and 1 - 3
* means filter # filterIndex - 1)
* @see "HAL_SetFilterSelect"
*/
public static native void setFilterSelect(int digitalPortHandle, int filterIndex);
/**
* Reads the filter index from the FPGA.
*
* <p>Gets the filter index used to filter out short pulses.
*
* @param digitalPortHandle the digital port handle
* @return the filter index (Must be in the range 0 - 3, where 0 means "none" and 1 - 3 means
* filter # filterIndex - 1)
* @see "HAL_GetFilterSelect"
*/
public static native int getFilterSelect(int digitalPortHandle);
/**
* Sets the filter period for the specified filter index.
*
* <p>Sets the filter period in FPGA cycles. Even though there are 2 different filter index
* domains (MXP vs HDR), ignore that distinction for now since it complicates the interface. That
* can be changed later.
*
* @param filterIndex the filter index, 0 - 2
* @param fpgaCycles the number of cycles that the signal must not transition to be counted as a
* transition.
* @see "HAL_SetFilterPeriod"
*/
public static native void setFilterPeriod(int filterIndex, int fpgaCycles);
/**
* Gets the filter period for the specified filter index.
*
* <p>Gets the filter period in FPGA cycles. Even though there are 2 different filter index
* domains (MXP vs HDR), ignore that distinction for now since it complicates the interface.
*
* @param filterIndex the filter index, 0 - 2
* @return The number of FPGA cycles of the filter period.
* @see "HAL_GetFilterPeriod"
*/
public static native int getFilterPeriod(int filterIndex);
/** Utility class. */
private DigitalGlitchFilterJNI() {}
}

View File

@@ -1,79 +0,0 @@
// Copyright (c) FIRST and other WPILib contributors.
// Open Source Software; you can modify and/or share it under the terms of
// the WPILib BSD license file in the root directory of this project.
#include <jni.h>
#include "HALUtil.h"
#include "edu_wpi_first_hal_DigitalGlitchFilterJNI.h"
#include "hal/DIO.h"
using namespace hal;
extern "C" {
/*
* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
* Method: setFilterSelect
* Signature: (II)V
*/
JNIEXPORT void JNICALL
Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_setFilterSelect
(JNIEnv* env, jclass, jint id, jint filter_index)
{
int32_t status = 0;
HAL_SetFilterSelect(static_cast<HAL_DigitalHandle>(id), filter_index,
&status);
CheckStatus(env, status);
}
/*
* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
* Method: getFilterSelect
* Signature: (I)I
*/
JNIEXPORT jint JNICALL
Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_getFilterSelect
(JNIEnv* env, jclass, jint id)
{
int32_t status = 0;
jint result =
HAL_GetFilterSelect(static_cast<HAL_DigitalHandle>(id), &status);
CheckStatus(env, status);
return result;
}
/*
* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
* Method: setFilterPeriod
* Signature: (II)V
*/
JNIEXPORT void JNICALL
Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_setFilterPeriod
(JNIEnv* env, jclass, jint filter_index, jint fpga_cycles)
{
int32_t status = 0;
HAL_SetFilterPeriod(filter_index, fpga_cycles, &status);
CheckStatus(env, status);
}
/*
* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
* Method: getFilterPeriod
* Signature: (I)I
*/
JNIEXPORT jint JNICALL
Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_getFilterPeriod
(JNIEnv* env, jclass, jint filter_index)
{
int32_t status = 0;
jint result = HAL_GetFilterPeriod(filter_index, &status);
CheckStatus(env, status);
return result;
}
} // extern "C"

View File

@@ -194,60 +194,6 @@ HAL_Bool HAL_IsPulsing(HAL_DigitalHandle dioPortHandle, int32_t* status);
* @return true if a pulse on some line is in progress
*/
HAL_Bool HAL_IsAnyPulsing(int32_t* status);
/**
* Writes the filter index from the FPGA.
*
* Set the filter index used to filter out short pulses.
*
* @param[in] dioPortHandle the digital port handle
* @param[in] filterIndex the filter index (Must be in the range 0 - 3, where
* 0 means "none" and 1 - 3 means filter # filterIndex
* - 1)
* @param[out] status Error status variable. 0 on success.
*/
void HAL_SetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t filterIndex,
int32_t* status);
/**
* Reads the filter index from the FPGA.
*
* Gets the filter index used to filter out short pulses.
*
* @param[in] dioPortHandle the digital port handle
* @param[out] status Error status variable. 0 on success.
* @return filterIndex the filter index (Must be in the range 0 - 3, where 0
* means "none" and 1 - 3 means filter # filterIndex - 1)
*/
int32_t HAL_GetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t* status);
/**
* Sets the filter period for the specified filter index.
*
* Sets the filter period in FPGA cycles. Even though there are 2 different
* filter index domains (MXP vs HDR), ignore that distinction for now since it
* complicates the interface. That can be changed later.
*
* @param[in] filterIndex the filter index, 0 - 2
* @param[in] value the number of cycles that the signal must not
* transition to be counted as a transition.
* @param[out] status Error status variable. 0 on success.
*/
void HAL_SetFilterPeriod(int32_t filterIndex, int64_t value, int32_t* status);
/**
* Gets the filter period for the specified filter index.
*
* Gets the filter period in FPGA cycles. Even though there are 2 different
* filter index domains (MXP vs HDR), ignore that distinction for now since it
* complicates the interface. Set status to NiFpga_Status_SoftwareFault if the
* filter values mismatch.
*
* @param[in] filterIndex the filter index, 0 - 2
* @param[out] status Error status variable. 0 on success.
* @return The number of FPGA cycles of the filter period.
*/
int64_t HAL_GetFilterPeriod(int32_t filterIndex, int32_t* status);
#ifdef __cplusplus
} // extern "C"
#endif

View File

@@ -269,32 +269,4 @@ HAL_Bool HAL_IsPulsing(HAL_DigitalHandle dioPortHandle, int32_t* status) {
HAL_Bool HAL_IsAnyPulsing(int32_t* status) {
return false; // TODO(Thad) Figure this out
}
void HAL_SetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t filterIndex,
int32_t* status) {
auto port = digitalChannelHandles->Get(dioPortHandle, HAL_HandleEnum::DIO);
if (port == nullptr) {
*status = HAL_HANDLE_ERROR;
return;
}
// mimics athena HAL
port->filterIndex = filterIndex % 4;
}
int32_t HAL_GetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t* status) {
auto port = digitalChannelHandles->Get(dioPortHandle, HAL_HandleEnum::DIO);
if (port == nullptr) {
*status = HAL_HANDLE_ERROR;
return 0;
}
return port->filterIndex;
}
void HAL_SetFilterPeriod(int32_t filterIndex, int64_t value, int32_t* status) {
// TODO(Thad) figure this out
}
int64_t HAL_GetFilterPeriod(int32_t filterIndex, int32_t* status) {
return 0; // TODO(Thad) figure this out
}
} // extern "C"

View File

@@ -201,25 +201,4 @@ HAL_Bool HAL_IsAnyPulsing(int32_t* status) {
return false;
}
void HAL_SetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t filterIndex,
int32_t* status) {
*status = HAL_HANDLE_ERROR;
return;
}
int32_t HAL_GetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t* status) {
*status = HAL_HANDLE_ERROR;
return 0;
}
void HAL_SetFilterPeriod(int32_t filterIndex, int64_t value, int32_t* status) {
*status = HAL_HANDLE_ERROR;
return;
}
int64_t HAL_GetFilterPeriod(int32_t filterIndex, int32_t* status) {
*status = HAL_HANDLE_ERROR;
return 0;
}
} // extern "C"