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https://github.com/wpilibsuite/allwpilib
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[hal, wpilib] Remove DigitalGlitchFilter (#7725)
This commit is contained in:
@@ -1,65 +0,0 @@
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// Copyright (c) FIRST and other WPILib contributors.
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// Open Source Software; you can modify and/or share it under the terms of
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// the WPILib BSD license file in the root directory of this project.
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package edu.wpi.first.hal;
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/**
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* Digital Glitch Filter JNI functions.
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*
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* @see "hal/DIO.h"
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*/
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public class DigitalGlitchFilterJNI extends JNIWrapper {
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/**
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* Writes the filter index from the FPGA.
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*
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* <p>Set the filter index used to filter out short pulses.
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*
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* @param digitalPortHandle the digital port handle
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* @param filterIndex the filter index (Must be in the range 0 - 3, where 0 means "none" and 1 - 3
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* means filter # filterIndex - 1)
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* @see "HAL_SetFilterSelect"
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*/
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public static native void setFilterSelect(int digitalPortHandle, int filterIndex);
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/**
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* Reads the filter index from the FPGA.
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*
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* <p>Gets the filter index used to filter out short pulses.
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*
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* @param digitalPortHandle the digital port handle
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* @return the filter index (Must be in the range 0 - 3, where 0 means "none" and 1 - 3 means
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* filter # filterIndex - 1)
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* @see "HAL_GetFilterSelect"
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*/
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public static native int getFilterSelect(int digitalPortHandle);
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/**
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* Sets the filter period for the specified filter index.
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*
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* <p>Sets the filter period in FPGA cycles. Even though there are 2 different filter index
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* domains (MXP vs HDR), ignore that distinction for now since it complicates the interface. That
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* can be changed later.
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*
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* @param filterIndex the filter index, 0 - 2
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* @param fpgaCycles the number of cycles that the signal must not transition to be counted as a
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* transition.
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* @see "HAL_SetFilterPeriod"
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*/
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public static native void setFilterPeriod(int filterIndex, int fpgaCycles);
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/**
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* Gets the filter period for the specified filter index.
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*
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* <p>Gets the filter period in FPGA cycles. Even though there are 2 different filter index
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* domains (MXP vs HDR), ignore that distinction for now since it complicates the interface.
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*
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* @param filterIndex the filter index, 0 - 2
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* @return The number of FPGA cycles of the filter period.
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* @see "HAL_GetFilterPeriod"
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*/
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public static native int getFilterPeriod(int filterIndex);
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/** Utility class. */
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private DigitalGlitchFilterJNI() {}
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}
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@@ -1,79 +0,0 @@
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// Copyright (c) FIRST and other WPILib contributors.
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// Open Source Software; you can modify and/or share it under the terms of
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// the WPILib BSD license file in the root directory of this project.
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#include <jni.h>
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#include "HALUtil.h"
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#include "edu_wpi_first_hal_DigitalGlitchFilterJNI.h"
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#include "hal/DIO.h"
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using namespace hal;
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extern "C" {
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/*
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* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
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* Method: setFilterSelect
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* Signature: (II)V
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*/
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JNIEXPORT void JNICALL
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Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_setFilterSelect
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(JNIEnv* env, jclass, jint id, jint filter_index)
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{
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int32_t status = 0;
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HAL_SetFilterSelect(static_cast<HAL_DigitalHandle>(id), filter_index,
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&status);
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CheckStatus(env, status);
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}
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/*
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* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
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* Method: getFilterSelect
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* Signature: (I)I
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*/
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JNIEXPORT jint JNICALL
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Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_getFilterSelect
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(JNIEnv* env, jclass, jint id)
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{
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int32_t status = 0;
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jint result =
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HAL_GetFilterSelect(static_cast<HAL_DigitalHandle>(id), &status);
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CheckStatus(env, status);
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return result;
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}
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/*
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* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
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* Method: setFilterPeriod
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* Signature: (II)V
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*/
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JNIEXPORT void JNICALL
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Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_setFilterPeriod
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(JNIEnv* env, jclass, jint filter_index, jint fpga_cycles)
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{
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int32_t status = 0;
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HAL_SetFilterPeriod(filter_index, fpga_cycles, &status);
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CheckStatus(env, status);
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}
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/*
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* Class: edu_wpi_first_hal_DigitalGlitchFilterJNI
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* Method: getFilterPeriod
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* Signature: (I)I
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*/
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JNIEXPORT jint JNICALL
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Java_edu_wpi_first_hal_DigitalGlitchFilterJNI_getFilterPeriod
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(JNIEnv* env, jclass, jint filter_index)
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{
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int32_t status = 0;
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jint result = HAL_GetFilterPeriod(filter_index, &status);
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CheckStatus(env, status);
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return result;
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}
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} // extern "C"
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@@ -194,60 +194,6 @@ HAL_Bool HAL_IsPulsing(HAL_DigitalHandle dioPortHandle, int32_t* status);
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* @return true if a pulse on some line is in progress
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*/
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HAL_Bool HAL_IsAnyPulsing(int32_t* status);
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/**
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* Writes the filter index from the FPGA.
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*
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* Set the filter index used to filter out short pulses.
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*
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* @param[in] dioPortHandle the digital port handle
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* @param[in] filterIndex the filter index (Must be in the range 0 - 3, where
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* 0 means "none" and 1 - 3 means filter # filterIndex
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* - 1)
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* @param[out] status Error status variable. 0 on success.
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*/
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void HAL_SetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t filterIndex,
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int32_t* status);
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/**
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* Reads the filter index from the FPGA.
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*
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* Gets the filter index used to filter out short pulses.
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*
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* @param[in] dioPortHandle the digital port handle
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* @param[out] status Error status variable. 0 on success.
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* @return filterIndex the filter index (Must be in the range 0 - 3, where 0
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* means "none" and 1 - 3 means filter # filterIndex - 1)
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*/
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int32_t HAL_GetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t* status);
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/**
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* Sets the filter period for the specified filter index.
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*
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* Sets the filter period in FPGA cycles. Even though there are 2 different
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* filter index domains (MXP vs HDR), ignore that distinction for now since it
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* complicates the interface. That can be changed later.
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*
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* @param[in] filterIndex the filter index, 0 - 2
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* @param[in] value the number of cycles that the signal must not
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* transition to be counted as a transition.
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* @param[out] status Error status variable. 0 on success.
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*/
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void HAL_SetFilterPeriod(int32_t filterIndex, int64_t value, int32_t* status);
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/**
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* Gets the filter period for the specified filter index.
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*
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* Gets the filter period in FPGA cycles. Even though there are 2 different
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* filter index domains (MXP vs HDR), ignore that distinction for now since it
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* complicates the interface. Set status to NiFpga_Status_SoftwareFault if the
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* filter values mismatch.
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*
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* @param[in] filterIndex the filter index, 0 - 2
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* @param[out] status Error status variable. 0 on success.
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* @return The number of FPGA cycles of the filter period.
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*/
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int64_t HAL_GetFilterPeriod(int32_t filterIndex, int32_t* status);
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#ifdef __cplusplus
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} // extern "C"
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#endif
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@@ -269,32 +269,4 @@ HAL_Bool HAL_IsPulsing(HAL_DigitalHandle dioPortHandle, int32_t* status) {
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HAL_Bool HAL_IsAnyPulsing(int32_t* status) {
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return false; // TODO(Thad) Figure this out
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}
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void HAL_SetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t filterIndex,
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int32_t* status) {
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auto port = digitalChannelHandles->Get(dioPortHandle, HAL_HandleEnum::DIO);
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if (port == nullptr) {
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*status = HAL_HANDLE_ERROR;
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return;
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}
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// mimics athena HAL
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port->filterIndex = filterIndex % 4;
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}
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int32_t HAL_GetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t* status) {
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auto port = digitalChannelHandles->Get(dioPortHandle, HAL_HandleEnum::DIO);
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if (port == nullptr) {
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*status = HAL_HANDLE_ERROR;
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return 0;
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}
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return port->filterIndex;
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}
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void HAL_SetFilterPeriod(int32_t filterIndex, int64_t value, int32_t* status) {
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// TODO(Thad) figure this out
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}
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int64_t HAL_GetFilterPeriod(int32_t filterIndex, int32_t* status) {
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return 0; // TODO(Thad) figure this out
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}
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} // extern "C"
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@@ -201,25 +201,4 @@ HAL_Bool HAL_IsAnyPulsing(int32_t* status) {
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return false;
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}
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void HAL_SetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t filterIndex,
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int32_t* status) {
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*status = HAL_HANDLE_ERROR;
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return;
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}
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int32_t HAL_GetFilterSelect(HAL_DigitalHandle dioPortHandle, int32_t* status) {
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*status = HAL_HANDLE_ERROR;
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return 0;
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}
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void HAL_SetFilterPeriod(int32_t filterIndex, int64_t value, int32_t* status) {
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*status = HAL_HANDLE_ERROR;
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return;
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}
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int64_t HAL_GetFilterPeriod(int32_t filterIndex, int32_t* status) {
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*status = HAL_HANDLE_ERROR;
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return 0;
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}
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} // extern "C"
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