mirror of
https://github.com/wpilibsuite/allwpilib
synced 2026-07-02 02:51:42 +00:00
Fixed voltage range checking and error message
Change-Id: I7ba05eb27f3d82bfd37f6b407fe39e0ab9cf5bf0
This commit is contained in:
@@ -3,7 +3,7 @@
|
||||
#define SAMPLE_RATE_TOO_HIGH 1
|
||||
#define SAMPLE_RATE_TOO_HIGH_MESSAGE "Analog module sample rate is too high"
|
||||
#define VOLTAGE_OUT_OF_RANGE 2
|
||||
#define VOLTAGE_OUT_OF_RANGE_MESSAGE "Voltage to convert to raw value is out of range [-10; 10]"
|
||||
#define VOLTAGE_OUT_OF_RANGE_MESSAGE "Voltage to convert to raw value is out of range [0; 5]"
|
||||
#define LOOP_TIMING_ERROR 4
|
||||
#define LOOP_TIMING_ERROR_MESSAGE "Digital module loop timing is not the expected value"
|
||||
#define SPI_WRITE_NO_MOSI 12
|
||||
|
||||
Reference in New Issue
Block a user