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Uses new FPGA calls to get 64 bit FPGA time and 64 bit PWM cycle start time. (#687)

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Thad House
2017-10-27 18:03:10 -07:00
committed by Peter Johnson
parent 4ab095e9c9
commit f34332643a
4 changed files with 37 additions and 35 deletions
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20
hal/src/main/native/athena/PWM.cpp
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@@ -450,4 +450,24 @@ int32_t HAL_GetLoopTiming(int32_t* status) {
return pwmSystem->readLoopTiming(status);
}
/**
* Get the pwm starting cycle time
*
* @return The pwm cycle start time.
*/
uint64_t HAL_GetCycleStartTime(int32_t* status) {
initializeDigital(status);
if (*status != 0) return 0;
uint64_t upper1 = pwmSystem->readCycleStartTimeUpper(status);
uint32_t lower = pwmSystem->readCycleStartTime(status);
uint64_t upper2 = pwmSystem->readCycleStartTimeUpper(status);
if (*status != 0) return 0;
if (upper1 != upper2) {
// Rolled over between the lower call, reread lower
lower = pwmSystem->readCycleStartTime(status);
if (*status != 0) return 0;
}
return (upper2 << 32) + lower;
}
} // extern "C"