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e73c8d06eb0f29c4f16a7d9979baaaa86e7ae3ad
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2 Commits

Author SHA1 Message Date
Thomas Clark
e73c8d06eb Fixed a few more small TODOs 
Timer::Get now compensates for the FPGA time rolling over after 71 minutes

UltraSonic::Ping doesn't bother disabling automatic mode, since it asserts
that it's not in automatic mode on the line before.

Change-Id: I6b0f45327c453abd8a846ec8da0f9676e210d909
 2014-08-04 15:25:41 -04:00
thomasclark
bb50f4b134 C++ testing 
Made a toplevel directory for C++ and C++ tests

Change-Id: I4bc2074a7036ec7fe79568b411637a5bee9eb5b3

Added the C++ testing framework and one test

Change-Id: I1e80a1e16b251a49666820a9d4c8caa025da9785
 2014-06-02 15:36:18 -04:00