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https://github.com/wpilibsuite/allwpilib
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e73c8d06eb0f29c4f16a7d9979baaaa86e7ae3ad
Timer::Get now compensates for the FPGA time rolling over after 71 minutes UltraSonic::Ping doesn't bother disabling automatic mode, since it asserts that it's not in automatic mode on the line before. Change-Id: I6b0f45327c453abd8a846ec8da0f9676e210d909
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WPILib - FRC Robotics Library
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